1. Field of the Invention
The present invention relates to a data processor performing a data process accompanied with an analog-digital conversion (AD conversion) and a solid-state imaging device, an imaging device, and an electronic apparatus as an example of a physical quantity distribution detecting semiconductor device employing the structure of the AD conversion. More particularly, the invention relates to a digital signal processing technique suitable for a physical quantity distribution detecting semiconductor device or other electronic apparatuses, such as a solid-state imaging device in which plural unit elements responding to externally input electromagnetic waves such as light or radiation are arranged so as to voluntarily select a physical quantity distribution converted into electrical signals by the unit elements under an address control and to read out the selected physical quantity distribution as an electrical signal. Specifically, the invention relates to a digital data acquiring technique for treating a processing signal.
2. Description of the Related Art
In recent years, as an example of a solid-state imaging device, MOS (Metal Oxide Semiconductor) or CMOS (Complementary MOS) image sensors capable of overcoming various problems which CCD (Charge Coupled Device) image sensor has attracted attention.
For example, a scheme of a so-called column-parallel output type or column type in which an amplifier circuit employing a floating diffusion amplifier is disposed for each pixel, a signal processing circuit is disposed at a stage in the back of a pixel array unit 10 for each column, a row in the pixel array unit is selected, the row is concurrently accessed to read a pixel signal from the pixel array unit in the unit of row, that is, concurrently in parallel from all the pixels in the row is widely used for the CMOS image sensors.
A scheme of converting an analog pixel signal read from the pixel array unit into digital data by the use of an analog-digital converter and then outputting the digital data to the outside may be employed for the solid-state imaging devices.
This is true in the column-parallel output type image sensors. Various signal output circuits have been invented and the most advanced example thereof is a scheme having an AD converter every column and taking out a pixel signal as digital data therefrom.
Various AD conversion schemes have been considered in view of circuit scale, processing speed (increase in speed) resolution, or the like. An example thereof is an AD conversion scheme comparing an analog unit signal with a so-called ramp type reference signal (ramp wave) of which the value gradually varies for conversion into digital data, performing a count process along with the comparison process, and acquiring digital data of the unit signal on the basis of a count value at the time of completion of the comparison process, which is called a slope integrating type or a ramp signal comparing type (hereinafter, referred to as a reference signal comparing type). By combining the reference signal comparing AD conversion scheme and the column-parallel output type scheme, the analog output from the pixels can be converted to a low band in an AD conversion manner by columns in parallel, which is suitable for an image sensor combining high speed with high image quality.
Here, regarding the pixel signal, a difference between a pixel signal level at the time of resetting the pixels and a pixel signal level at the time of reading signal charges is a true signal component. Accordingly, when the reference signal comparing AD conversion scheme is used, a structure in which a difference process in any one side is considered is employed. A structure for performing a difference process together at the time of concurrently converting the pixel signal from all the pixels in a row into digital data by combination of the reference signal comparing AD conversion scheme and the column-parallel output type is employed.
For example, a solid-state imaging device mounted with a column-parallel type AD converter is disclosed in JP-A-2005-278135 and W. Yang et al., “An Integrated 800×600 CMOS Image System,” ISSCC Digest of Technical Papers, pp. 304-305, February, 1999.
In the structure described in W. Yang et al., a master counter is disposed outside a column area, the bit output of the counter is drawn into the column area, and AD converted data based on a signal amplitude is acquired every column in the column area by performing a count process depending on a voltage level of a pixel signal by columns and then latching (storing) a counter output of the column. In the structure described in Yang et al., the AD conversion result of a pixel signal voltage level (reset level) at the time of resetting pixels and the AD conversion result of a pixel signal voltage level (signal level) at the time of reading signal charges are stored in different data storages, a set of the AD conversion results is transmitted to a subtraction circuit at the subsequent stage through a horizontal signal line, and the set of AD conversion results is subjected to a difference process by the subtraction circuit.
In the structure described in JP-A-2005-278135, a counter is disposed every column in a column area and AD converted data based on a signal amplitude is acquired every column by performing a count process depending on a voltage level of a pixel signal by columns and then latching (storing) a counter output of the column. In the structure described in JP-A-2005-278135, by switching a count mode between an up-count mode and a down-count mode at the time of a reset level AD conversion and at the time of a signal level AD conversion, the AD conversion result of a true signal component is automatically acquired as the final AD conversion output value at the time of the signal level AD conversion which is the second AD conversion process. That is, a difference processing function is carried out at the same time of the AD conversion process.